1. Technical Field
The present invention relates to photolithographic printing in general, and, in particular, to a method and system for performing optical proximity correction with process variations considerations.
2. Description of Related Art
When transferring an integrated circuit design pattern onto a semiconductor substrate, the most common technique is to produce a photomask with a photomask layout of the integrated circuit design, and then a lithography process is utilized to expose the patterns of the photomask layout to a semiconductor substrate in a predetermined ratio.
As integrated circuit designs become more complex, the number of circuit elements to be produced on a wafer become increasingly large and each object becomes correspondingly smaller. As the size of the objects to be produced become similar in size or smaller than the wavelength of light used to illuminate the wafer, distortions occur whereby the pattern of objects formed on the wafer do not correspond to the pattern of objects defined by the mask. One objective criterion for defining how well an image is formed or an object is produced is the edge placement error (EPE) that indicates how far an edge of an object is shifted from its desired position. Another objective criterion is the edge contrast or slope that describes how sharply the image intensity changes from exposed to not exposed, or vice versa.
In order to improve the manufacturability of target layout designs, optical process correction (OPC) techniques have been developed that alter a mask layout pattern in order to correctly create the desired pattern of objects on a wafer. The conventional OPC method of improving the fidelity of a layout is to simulate how a pattern of polygon fragments fabricated on a mask will be lithographically reproduced as corresponding edges on the wafer, and then moves the fragment such that the edge on the wafer will be created at the proper location.
In a typical OPC procedure, a target layout includes several polygons that represents the objects desired on the wafer. Referring now to the drawings and in particular to FIG. 1A, there is illustrated a fragmented polygon in a target layout. As shown, a polygon 10 is divided up into edges 12a-12f. For each of edges 12a-12f, at least one control point (or simulation site) is designated. For example, a control point 13c is designated to edge 12c, and a control point 13d is designated to edge 12d. Although there is typically one site per edge, some edges may have more than one simulation site.
Simulations are generated at each of the sites of the edges, usually along a cut line perpendicular to the edge, and measurements of the predicted image slope, maximum and minimum intensities are calculated as shown in FIG. 1B. From these image parameters, the actual placement of the edge is predicted using techniques such as the variable threshold resist model. The edge location as predicted and the location of the ideal edge in the target layout are then compared in order to calculate the difference as an edge placement error (EPE).
Changes are then made in the mask layout to minimize the calculated EPE. For each edge, a fragment in the mask layout is designated, and each mask fragment is moved in an attempt to reduce the calculated EPE. New simulations at the sites are generated again from the revised mask layout, and new EPEs are calculated. This procedure is repeated iteratively until EPE falls within an acceptable tolerance value.
Conventional model-based OPC assumes nominal process conditions without considering any process variations due to the current lack of variational lithography models. However, disregarding process variations may lead to erroneous timing, power and yield characterization analysis. For example, post-OPC silicon image based timing analysis is found to be substantially different from that based on the drawn layout.
Consequently, it would be desirable to provide an improved method and system for performing OPC with process variations considerations.